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Table 8.11. DMA cycle of 12 bytes using a halfword increment
Initial values of channel_cfg, prior to the DMA cycle
src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11
End Pointer
0x5E7
0x5E7
Count
11
10
Difference
0x16
0x14
1
Address
0x5D1
0x5D3
DMA transfers
0x5E7
0x5E7
0x5E7
0x5E7
0x5E7
0x5E7
9
8
7
6
5
4
0x12
0x10
0xE
0xC
0xA
0x8
0x5D5
0x5D7
0x5D9
0x5DB
0x5DD
0x5DF
Values of channel_cfg after 2 DMA transfers
R
src_size = b00, dst_inc = b01, n_minus_1 = b011, cycle_ctrl = 1, R_power = b11
End Pointer
0x5E7
0x5E7
Count
3
2
Difference
0x6
0x4
Address
0x5E1
0x5E3
DMA transfers
0x5E7
0x5E7
1
0
0x2
0x0
0x5E5
0x5E7
src_size = b00, dst_inc = b01, n_minus_1 = 0, cycle_ctrl = 0 , R_power = b11
This value is the result of count being shifted left by the value of dst_inc.
After the controller completes the DMA cycle it invalidates the channel_cfg memory location by clearing the cycle_ctrl field.
Final values of channel_cfg, after the DMA cycle
2
1
2
8.4.4 Interaction with the EMU
The DMA interacts with the Energy Management Unit (EMU) to allow transfers from e.g. the LEUART
to occur in EM2. The EMU can wake up the DMA sufficiently long to allow data transfers to occur. See
section "DMA Support" in the LEUART documentation.
8.4.5 Interrupts
The PL230 dma_done[n:0] signals, one for each channel, as well as the dma_err signal, are available as
interrupts to the Cortex-M3 core. They are combined into one interrupt vector, DMA_INT. If interrupts for
the DMA is enabled in the ARM Cortex-M3 core, an interrupt will be made if one or more of the interrupt
flags in DMA_IF and their corresponding bits in DMA_IEN are set.
8.5 Examples
A basic example of how to program the DMA for transferring 42 bytes from the USART1 to
memory location 0x20003420. Assumes that the channel 0 is currently disabled, and that the
DMA_ALTCTRLBASE register has already been configured.
2011-04-12 - d0001_Rev1.10
57
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